Buried contacts have been extensively used in CMOS memory circuits. A CMOS SRAM cell employing a load resistor and cross-coupled transistors utilizes buried contacts to connect each gate electrode to the drain of the opposing cross-coupled transistor. In a typical cell layout, the active regions of the cross-coupled transistors also serve as the drain regions of pass transistors which provide access from the bit lines to the memory cell. The buried contacts provide a means of making an electrical connection between the polysilicon gates and the common active region of the cross-coupled and pass transistors. Additionally, to facilitate the construction of a gate-lead cross over, the electrical path of one of the leads is re-routed to the substrate using a buried contact.
A typical process sequence for the formation of a buried contact, in accordance with the prior art, is illustrated in FIGS. 1a through 1c. Shown in FIG. 1a, in cross section, is a P-type semiconductor substrate 5 having undergone some of the process steps in the fabrication of a semiconductor device. A gate oxide layer 7 overlying the surface of substrate 5 is patterned using resist mask 8 and etched to form an opening 9 exposing a portion of the substrate for the formation of a buried contact. An ion implantation is performed to create an N-type drain region 10 in substrate 5 using resist mask 8 as an implant mask. Resist mask 8 is removed and a layer of polysilicon 12 is then conformably deposited onto substrate 5 as shown in FIG. 1b. Subsequently, polysilicon layer 12 is patterned and etched, by reactive ion etching, to form a transistor gate electrode 14 making electrical contact 15 with drain region 10, as shown in FIG. 1c. Electrode 14 can also be a polysilicon extension of a remote transistor gate electrode, for example, as in a CMOS SRAM cell. A trench 16 has been formed in substrate 5 during the etching process used to form gate electrode 14 because of the poor selectivity of the etch process. The selectivity of an etch process is defined as the ratio of the etch rates of the material to be etched versus the underlying material. The reactive ion etch gases used to etch polysilicon layer 12 will also etch the single crystal silicon of substrate 5 at about the same rate, or equivalently, the selectivity of polysilicon to single crystal silicon is about 1:1. The formation of trench 16 is undesirable because a pathway is now present for charge leakage to occur between the P-type substrate and N-type drain region 10.
An additional problem associated with the formation of trench 16 is the uneven substrate surface topography created adjacent to contact 15, as illustrated in FIG. 1c. The additional topographic contrast presented by trench 16 can result in poor overlay continuity of subsequently formed electrical leads. The topographic discontinuity problem can become even more severe if sidewall spacers are formed, for example, as in a lightly-doped drain (LDD) formation process.